Hardware Technical Program Manager

Job description

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution

We are looking for a  Hardware Technical Program Manager to own the program end-to-end — from architecture freeze through RTL, verification, physical implementation, tapeout, bring-up, and production release.

You will be the operational center of the program: building and defending the schedule, driving the critical path, surfacing risk early, and making the tradeoff conversations happen before they become slips. You'll work daily with architecture, RTL design, DV/emulation, DFT, physical design, package, firmware, and the foundry/IP vendor ecosystem. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

Own the Program - Own the   silicon schedule from architecture freeze through tapeout, bring-up, and production with  the schedule informed by customer requirements and internal functional leads. - Drive the weekly execution cadence (program reviews, design reviews, tapeout readiness) and maintain a single source of truth for status, dependencies, and decisions.

Drive Cross-Functional Execution - Coordinate handoffs across architecture, RTL, DV/emulation, DFT, physical design, IP, package, and software - Manage the dependency chains hardware programs live and die on: IP delivery, PDK/library releases, EDA versions, and emulation capacity. - Run the tapeout checklist and signoff matrix (timing, power, IR/EM, DRC/LVS, DFT coverage, ECO closure, GDS handoff), holding owners to closure criteria. - Work with supply chain/logistics for: IP acquisition, silicon arrival, ATE/loadboard readiness, lab scheduling, bug triage, and ECO/respin decision support.

Manage Risk & Decisions - Surface risk early with mitigation options and schedule impact quantified — late IP, coverage shortfalls, convergence misses, foundry slot changes. - Facilitate PPA, schedule, and scope tradeoffs, and document what was decided, by whom, and why.

Coordinate Externally & Report Up - Interface with foundry, OSAT, IP, and EDA partners on deliverables, technology file releases, mask slots, and escalations; support export control/ECCN compliance with legal and operations. - Deliver crisp executive reporting — where the program stands, what's at risk, what decision is needed and by when — across distributed teams and time zones. - Track resource allocation and NRE/mask/license/prototype budgets against program needs.

Required Qualifications - B.S. in Electrical/Computer Engineering, Computer Science, or equivalent; M.S. or MBA a plus. - 7+ years in semiconductor/hardware engineering or program management, including at least 2 full SoC/ASIC programs taken from concept through tapeout and silicon bring-up . - Working fluency in the chip design flow: RTL, functional verification and coverage closure, DFT, synthesis, PnR, STA, physical signoff (DRC/LVS/IR/EM), GDSII handoff, and post-silicon validation. - Demonstrated ability to build and defend a bottoms-up schedule with critical path analysis and dependency mapping. - Track record influencing without authority — earning the technical credibility to push senior engineers on commitments and dates. - Strong written and verbal communication; able to run a room of principal engineers and an exec review with equal effectiveness. - Hands-on with program tooling: Jira, Confluence, MS Project/Smartsheet, and familiarity with the Synopsys/Cadence/Siemens EDA ecosystem.

Desired Qualifications & Experience Requirements   - Prior hands-on engineering experience in design, DV, or physical design before moving to program management. - Experience on advanced or FinFET nodes (16/12/7nm or more advanced) and direct foundry engagement (TSMC preferred). - Familiarity with AI/ML accelerators, dataflow or novel compute architectures.. - Experience managing emulation/FPGA prototyping programs and pre-silicon software enablement timelines. - Exposure to package/board co-design programs (FC-BGA, WLCSP) and OSAT coordination. - Experience with EVK/reference board programs and customer/FAE enablement schedules. - Familiarity with quality and compliance frameworks relevant to the target market (automotive, industrial, or security certifications).

We offer a competitive base salary for this role, generally ranging from $200,000 to $260,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate.

Why Join Efficient?

Efficient offers a   competitive compensation and benefits package , including   401K match, company-paid benefits, equity program, paid parental leave, and flexibility . We are committed to personal and professional development and strive to grow together as people and as a company.